1. Field of the Invention
The invention relates to integrated circuits including field programmable gate array (FPGA) and other programmable logic device (PLD) architectures and to optimization methods for such integrated circuits. More specifically, the invention relates to a method to compensate for disparate signal rise and fall times to improve timing and power performance in an integrated circuit.
2. The Prior Art
One kind of logic block widely used in FPGA architectures is a look-up table (LUT). The input and output pins on a LUT logic block can be programmed to either polarity. Specifically, the output of a LUT logic block can be inverted by inverting all the bits in the LUT truth table. An input pin of a LUT logic block can be inverted by swapping the bits in the LUT truth table controlled by the input pin.
The interconnect network of an FPGA architecture is usually implemented using routing multiplexers. As process geometry decreases, it becomes increasingly necessary to insert buffers at the outputs of the routing multiplexers, especially the routing multiplexers driving loads over long metal lines. A buffer is implemented as a cascaded inverter chain. The rise and fall times of a buffer are strongly related to the sizes of the p-type and n-type transistors in the inverters of the buffer. In the prior art, integrated circuit designers generally choose the ratio of the size of p-type and n-type transistors such that the difference in rise and fall times is minimized.
Synthesis is a step in the software flow in which a logic netlist is transformed to a form (such as a set of LUTs) that can be more readily implemented in FPGA. Placement and routing are two steps in implementing a user design in a programmable logic device. Placement is the step in the software flow in which the units of logic netlist (such as LUTs) are assigned to specific locations on an FPGA device.
Routing is the step in the software flow in which the connections between logic units in a netlist are realized using the interconnection wires in an FPGA device. Timing analysis is a step in the software flow in which a netlist implemented in an FPGA device is analyzed to estimate the speed at which the circuit described by the netlist can perform, and to develop other information that is useful for the FPGA users.
Meeting the timing constraints in design is an essential objective of FPGA software tools. The state-of-the-art flow for achieving this objective is shown in FIG. 1A and includes timing-driven synthesis (shown at reference numeral 10); timing-driven clustering (typically for cluster-based FPGA architecture) (shown at reference numeral 12); timing-driven placement (shown at reference numeral 14); and timing-driven routing (shown at reference numeral 16). Timing analysis (shown at reference numeral 18) is performed to verify the design.
Persons skilled in the art will note that none of the steps in the flow attempt to further improve timing by selecting optimal output polarity supported by the FPGA architecture.